Package structure and manufacturing method thereof

ABSTRACT

A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention generally relates to a package structure, inparticular, to a manufacturing method of a package structure usingsacrificial structures for wire bonding.

2. Description of Related Art

In order for electronic product design to achieve being light, slim,short, and small, semiconductor packaging technology has keptprogressing, in attempt to develop products that are smaller in volume,lighter in weight, higher in integration, and more competitive inmarket. For example, integrated fan-out packages have becomeincreasingly popular due to their compactness. However, in currentfan-out package designs, if a package requires multi-chip stacking, tworedistribution layers (RDL) and big pillars are generally required toprovide the connection. For such package designs, the manufacturingprocess is usually complicated, time consuming and an issue of warpagealso exist. Therefore, a simplified method/design having lowerproduction cost is desired.

SUMMARY OF THE INVENTION

The invention provides a package structure and a manufacturing methodthereof, which uses sacrificial structures to fix the location of a wirefor wire bonding. The method effectively reduces the size andmanufacturing cost of the package, and overcomes the issue of wafer orpanel warpage.

The invention provides a manufacturing method of a package structure.The method includes at least the following steps. A carrier is provided.A semiconductor die and a sacrificial structure are disposed on thecarrier. The semiconductor die is electrically connected to bonding padson the sacrificial structure through a plurality of conductive wires. Asencapsulant is formed on the carrier to encapsulate the semiconductordie, the sacrificial structure and the conductive wires. The carrier isdebonded, and the sacrificial structure is removed through a thinningprocess to reveal the bonding pads or the conductive wires. Aredistribution layer is formed on the semiconductor die and theencapsulant. The redistribution layer is electrically connected to thesemiconductor die through the conductive wires.

The invention further provides a package structure including anencapsulant, a stacked die, a plurality of bonding pads, a plurality ofconductive wires, and a redistribution layer. The encapsulant has a topsurface and a bottom surface opposite to the top surface. The stackeddie is embedded in the encapsulant. The bonding pads are embedded in theencapsulant, wherein the bonding pads are exposed on a top surface ofthe encapsulant. The conductive wires are embedded in the encapsulant,wherein the stacked die is electrically connected to the bonding padsthrough the conductive wires. The redistribution layer is disposed onthe stacked die and on the top surface of the encapsulant, wherein theredistribution layer is electrically connected to the stacked diethrough the bonding pads and the conductive wires.

Based on the above, a sacrificial structure is used to fix the positionof the conductive wires. As such, when removing the sacrificialstructure, the precise location of the wire or weld may be provided forfurther connection. In addition, a thickness of the semiconductor diemay be effectively controlled during the thinning process, thus anoverall size of the package structure may be reduced. Furthermore, withthe presence of the sacrificial structure, an area ratio between thedies and the encapsulant is decreased. Thus, the issue of wafer or panelwarpage may be resolved. Overall, the simplicity of the manufacturingprocess of the package structure may be realized, thereby reducing themanufacturing cost.

To make the above features and advantages of the present invention morecomprehensible, several embodiments accompanied with drawings aredescribed in detail as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1A to FIG. 1G are schematic cross-sectional views illustrating amanufacturing method of a package structure according to an embodimentof the invention.

FIG. 2A to FIG. 2G are schematic cross-sectional views illustrating amanufacturing method of a package structure according to an embodimentof the invention.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

FIG. 1A to FIG. 1G are schematic cross-sectional views illustrating amanufacturing method of a package structure according to an embodimentof the invention. Referring to FIG. 1A, a carrier 102 is provided. Thecarrier 102 may be a glass substrate or a glass supporting board. Insome embodiments, other suitable substrate material may be adapted asthe carrier 102 as long as the material is able to withstand thesubsequent processes while carrying the package structure formedthereon.

The sacrificial structures 104B are disposed on the carrier 102. Thesacrificial structures 104B are, for example, a sacrificial layer to beremoved in a subsequent process. Thus, a material of the sacrificiallayer is not particularly limited, as long as it can be removed througha thinning process described thereafter. The sacrificial structures 104Bare disposed on the carrier 102 through an adhesive layer 103 located onthe carrier 102. In some embodiments, the adhesive layer 103 may be adie attach film or formed from adhesive materials including an epoxyresin. The adhesive layer 103 may be formed by methods such as coating,inkjet printing, film attaching or other suitable methods for providinga structural support to eliminate the need for mechanical clampingbetween the sacrificial structures 104B and the carrier 102.

The semiconductor die 104A is disposed on the carrier 102, and locatedon the sacrificial structures 104B. In the present embodiment, thesemiconductor die 104A is, for example stacked dies that comprise atleast a bottom semiconductor die and a top semiconductor die stacked ontop of each other. For instance, as shown in FIG. 1A, the semiconductordie 104A includes a first semiconductor die 104A-1, a secondsemiconductor die 104A-2 and a third semiconductor die 104A-3 stacked ontop of each other. The first semiconductor die 104A-1 serve as thebottom semiconductor die, while the third semiconductor die 104A-3 serveas the top semiconductor die, while the second semiconductor die 104A-2is sandwiched therebetween. However, it construes no limitation in theinvention. The number of stacked dies in the semiconductor die 104A isnot particularly limited. In some embodiments, a die attach film (DAF;not illustrated) may be disposed between each of the stacked dies toenhance their adhesion. Furthermore, in the present embodiment, thesemiconductor die 104A is, for example, an ASIC (Application-SpecificIntegrated Circuit). However, it construes no limitation in theinvention. Other suitable active devices may also be utilized as thesemiconductor die 104A.

As shown in FIG. 1A, a width W2 of the sacrificial structure 104B isgreater than a width W1 of the semiconductor die 104A. In the case forstacked dies, the width W2 of the sacrificial structure 104B is greaterthan a width of each of the semiconductor dies (104A-1, 104A-2 and104A-3). The semiconductor die 104A or the stacked dies each have afirst surface Y1 facing the carrier 102 and a second surface Y2 facingaway from the carrier 102. Furthermore, bonding pads 105 are provided onthe sacrificial structures 104B, and provided on the second surfaces Y2of the semiconductor die 104A (stacked dies). The bonding pads 105 are,for example, aluminum pads or any other suitable material used for wirebonding. In some embodiments, the bonding pads 105 can be embeddedwithin the sacrificial structures 104B.

Furthermore, as shown in FIG. 1A, a plurality of conductive wires 106 isprovided to electrically connect the bonding pads 105 of thesemiconductor die 104A to the bonding pads 105 of the sacrificialstructures 104B. The conductive wires 106 are, for example, used forwire bonding, and have a curved three-dimensional structure. In someembodiments, the conductive wires 106 are formed after stacking severaldies in a group. For example, for multi-die stacking, the conductivewires 106 are used to provide electrical connection after two to fourdies are stacked. For instance, in the embodiment shown in FIG. 1A,after disposing the first semiconductor die 104A-1 on the sacrificialstructures 104B, and disposing the second semiconductor die 104A-2 onthe first semiconductor die 104A-1, the conductive wires 106 are used toelectrically connect the bonding pads 105 on the stacked semiconductordies (104A-1 and 104A-2) to the bonding pads 105 on the sacrificialstructure 104B. The process is repeated until all dies are stacked andthe electrical connection is established. In some alternativeembodiments, the conductive wires 106 are formed after all dies (104A-1,104A-2 and 104A-3) are stacked.

Referring to FIG. 1B, after wire bonding, an encapsulant 108 is formedon the carrier 102 to encapsulate the semiconductor die 104A, thesacrificial structure 104B and the conductive wires 106. Thesemiconductor die 104A, the sacrificial structures 104B and theconductive wires 106 are completely encapsulated by the encapsulant 108.In some embodiments, the encapsulant 108 may be a molding compoundformed by molding processes. However, in some alternative embodiments,the encapsulant 108 may be formed by an insulating material such asepoxy or other suitable resins. In general, when an area ratio of a dieto an encapsulant is low, a problem of wafer or panel warpage may occur.As shown in FIG. 1B, by having the sacrificial structure 104B serving asa base structure, an area ratio of the dies (sacrificial structure asdummy die plus the semiconductor die) to the encapsulant 108 isincreased. As such, an issue of wafer or panel warpage may be resolved.

Referring to FIG. 1C, the carrier 102 is debonded. That is, the carrier102 is separated from the encapsulant 108, the semiconductor die 104A,and sacrificial structures 104B. In some alternative embodiments, inorder to enhance the releasability of the semiconductor die 104A andsacrificial structures 104B from the carrier 102, a de-bonding layer(not illustrated) may be disposed on the carrier 102 before disposingthe dies (104A/104B) on the carrier 102. The de-bonding layer is, forexample, a light to heat conversion (LTHC) release layer or othersuitable release layers.

Referring to FIG. 1D, after debonding the carrier 102, the sacrificialstructures 104B are removed by a thinning process to reveal/expose theconductive wires 106. Specifically, connection terminals CT of theconductive wires 106 are exposed. In the present embodiment, connectionterminals CT may refer to end portions of the conductive wires 106 thatare available for further connection. However, it construes nolimitation in the invention. In alternative embodiments, the connectionterminals CT can be the bonding pads 105 or studs of the conductivewires 106 that are used for further connection. That is, the connectionterminals CT are generally treated as “connection points” that connectthe conductive wires 106 to a redistribution layer 110 formedthereafter. Wherein, the bonding pads 105 or studs of the conductivewires 106 may have a surface area greater than an area of the crosssection of the conductive wires 106.

Referring back to FIG. 1D, the thinning process may be performed throughmechanical grinding, chemical mechanical polishing (CMP), or othersuitable processes. After the thinning process, the connection terminalsCT of the revealed conductive wires 106 are coplanar with a firstsurface S1 of the semiconductor die 104A. In some embodiments, thethinning process may remove portions of the semiconductor die 104A toform a thinned semiconductor die 104A. For example, in the presentembodiment, a portion of the first semiconductor die 104A-1 (or bottomsemiconductor die) is partially removed by the thinning process, so thatthe connection terminals CT (of the conductive wires 106) are coplanarwith the first surface S of the first semiconductor die 104A-1 (bottomsemiconductor die). In other words, a thickness of the firstsemiconductor die 104A-1 is reduced. In particular, referring to FIG.1C, the first semiconductor die 104A-1 have a thickness of T1 before thethinning process, whereas in FIG. 1D, a thickness of the firstsemiconductor die 104A-1 reduces to T2 after the thinning process. Fromthe present embodiment, the thickness of the semiconductor die 104 maybe reduced during the thinning process. However, it construes nolimitation in the invention. In other embodiments, the thickness of thesemiconductor die 104A does not change after the thinning process. Inalternative embodiments, the thickness of the semiconductor die 104A maybe adjusted based on requirement during the thinning process.

As shown in FIG. 1D, the bonding pads 105 on the sacrificial structures104B are removed by the thinning process to reveal the conductive wires106 underneath. That is, the end portions of the conductive wires 106are treated as the connection terminals CT. However, it construes nolimitation in the invention. In alternative embodiments, the bondingpads 105 on the sacrificial structures 104B remain after the thinningprocess. In such embodiments, the thinning process is performed toreveal the bonding pads 105 on the sacrificial structures 104B, and therevealed portions of the bonding pads 105 serve as the connectionterminals CT. Furthermore, the sacrificial structures 104B may becompletely removed by the thinning process or residual amounts of thesacrificial structures 104B may remain after the thinning process.

Referring to FIG. 1E, after removing the sacrificial structures 104Bthrough the thinning process, a redistribution layer 110 is formed onthe semiconductor die 104A and the encapsulant 108. The redistributionlayer 110 may include a plurality of conductive elements 110A and aplurality of dielectric layers 110B alternately formed and stacked ontop of each other. As illustrated in FIG. 1E, the redistribution layer110 includes four dielectric layers 110B. However, the number of thedielectric layer 110B is not limited and may be adjusted based oncircuit design. The conductive elements 110A may include a plurality oftrace layers and a plurality of interconnect structures connecting thetrace layers. Furthermore, in the present embodiment, the redistributionlayer 110 is formed on the first surface S1 of the semiconductor die104A (stacked die). The redistribution layer 110 is electricallyconnected to the semiconductor die 104A through the conductive wires 106at the connection terminals CT. In particular, the conductive wires 106are electrically connected to the conductive elements 110A of theredistribution layer 110 through the connection terminals CT. Conductiveterminals 118 are then formed on the redistribution layer 110, and beingelectrically connected to the conductive elements 110A. The conductiveterminals 118 may be a plurality of under-ball metallurgy (UBM) patternsfor ball mount or connection pads for mounting of passive components.

Referring to FIG. 1F, after the formation of the redistribution layer110 and the conductive terminals 118, a plurality of conductive balls120 are placed onto the conductive terminals 118, and one or morepassive components 115 may be mounted on the conductive terminals 118.The conductive terminals 118 and the conductive balls 120 may, forexample, be formed by a ball placement process and a reflow process. Thepassive components 115 may be mounted on the conductive terminals 118through a soldering process. Examples of the passive components 115include capacitors, resistors, inductors, fuses, or antennas. However,they construe no limitation in the invention. After placing theconductive balls 120 and the passive components 115 on the conductiveterminals 118, a dicing or singulation process is performed on thepackage structure illustrated in FIG. 1F to render a plurality ofindividual packages 100 as shown in FIG. 1G. The dicing process is, forexample, performed at the dicing line DL for singulation of theindividual packages 100.

FIG. 2A to FIG. 2G are schematic cross-sectional views illustrating amanufacturing method of a package structure according to an embodimentof the invention. The embodiments shown in FIG. 2A to FIG. 2G aresimilar to the embodiments shown in FIG. 1A to FIG. 1G, therefore, thesame reference numerals are used to refer to the same or like parts, andtheir detailed descriptions are omitted herein. The difference betweenthe embodiments shown in FIG. 2A to FIG. 2G and the embodiments shown inFIG. 1A to FIG. 1G is in the position/design of the sacrificialstructures 104B.

As shown in FIG. 2A, the semiconductor die 104A and at least onesacrificial structure 104B are disposed on the carrier 102. In theexemplary embodiment, a plurality of the sacrificial structures 104B aredisposed on the carrier 102 to surround the semiconductor die 104A.Moreover, the semiconductor die 104A and the sacrificial structures 104Bare disposed on a same plane and on a same surface 102A of the carrier102. In the present embodiment, a width (W2/W3) of the sacrificialstructures 102B is smaller than a width W1 of the semiconductor die104A. The plurality of sacrificial structures 102B may have differentwidths W2 and W3. However, both of the widths W2 and W3 are smaller thanthe width W1 of the semiconductor die 104A. Furthermore, a thickness K2of the sacrificial structures 104B is smaller than a thickness K1 of thesemiconductor dies 104A. The thickness K1 of the semiconductor dies 104Arefers to the thickness of the first semiconductor die 104A-1 (bottomsemiconductor die) of the stacked dies. In the present embodiment, thesacrificial structures 104B is also a sacrificial layer that is removedthereafter. In other words, a thickness difference X1 between thesemiconductor die 104A and the sacrificial structures 104B (K1-K2) willdetermine a thickness of a thinned semiconductor die 104A formedthereafter.

Similar to the embodiments shown in FIG. 1A, bonding pads 105 may beformed on the semiconductor dies 104A and the sacrificial structures104B to allow for wire bonding. The wire bonding process is, forexample, performed after the stacking of several dies in a group, orperformed after stacking of all of the dies. In addition, passivecomponents 115 may be disposed on the sacrificial structures 104B. Forexample, the passive components 115 may be adjacent to the bonding pads105 and may be disposed on the same surface of the sacrificialstructures 104B. Furthermore, a plurality of conductive wires 106 isprovided to electrically connect the bonding pads 105 of thesemiconductor die 104A to the bonding pads 105 of the sacrificialstructures 104B.

Referring to FIG. 2B, similar to the embodiment shown in FIG. 1B, anencapsulant 108 is formed on the carrier 102 to encapsulate thesemiconductor die 104A, the sacrificial structure 104B and theconductive wires 106. However, in the embodiment shown in FIG. 2B, theencapsulant 108 further encapsulates the passive components 115. Thesemiconductor die 104A, the sacrificial structures 104B, the conductivewires 106 and the passive components 115 are completely encapsulated bythe encapsulant 108. As shown in FIG. 2B, by having the sacrificialstructures 104B surrounding the semiconductor die 104A, an area ratio ofthe die (semiconductor dies and sacrificial dummy dies) to theencapsulant 108 is increased. As such, an issue of wafer or panelwarpage may be resolved.

Referring to FIG. 2C, after formation of the encapsulant 108, thecarrier 102 are debonded. That is, the carrier 102 is separated from theencapsulant 108, the semiconductor die 104A, and sacrificial structures104B. In some alternative embodiments, in order to enhance thereleasability of the semiconductor die 104A and sacrificial structures104B from the carrier 102, a de-bonding layer (not illustrated) may bedisposed on the carrier 102 before disposing the dies (104A/104B) on thecarrier 102. The de-bonding layer is, for example, a light to heatconversion (LTHC) release layer or other suitable release layers.

Referring to FIG. 2D, after debonding the carrier 102, the sacrificialstructures 104B are removed by a thinning process to reveal/expose thebonding pads 105 on the sacrificial structures 104B. That is, a revealedportion of the bonding pads 105 serve as the connection terminals CT.However, it construes no limitation in the invention. In alternativeembodiments, the connection terminals CT can be the end portions (orstuds) of the conductive wires 106. That is, the thinning process isperformed to reveal/expose the end portions of the conductive wires 106.As noted above, connection terminals CT are generally treated as“connection points” that connect the conductive wires 106 to aredistribution layer 110 formed thereafter. Therefore, the connectionterminals CT will apply to all embodiments, and its position may bealtered depending on which portion is revealed (wires/pads) forconnection.

As shown in FIG. 2D, after the thinning process, the connectionterminals CT of the bonding pads 105 are coplanar with a first surfaceS1 of the semiconductor die 104A. In particular, a portion of the firstsemiconductor die 104A-1 (or bottom semiconductor die) is removed by thethinning process, so that the connection terminals CT are coplanar withthe first surface S1 of the first semiconductor die 104A-1 (bottomsemiconductor die). Moreover, a thickness 104T of the thinnedsemiconductor die (first semiconductor die 104A-1) will correspond to athickness difference X1 (see FIG. 2A) between the semiconductor die 104A(first semiconductor die 104A-1) and the sacrificial structure 104Bbefore the thinning process.

Referring to FIG. 2E, after removing the sacrificial structures 104Bthrough the thinning process, a redistribution layer 110 is formed onthe semiconductor die 104A and the encapsulant 108. The redistributionlayer 110 of FIG. 2E is similar to the redistribution layer 110 of FIG.1E, hence its detailed description is omitted herein. In the presentembodiment, the redistribution layer 110 is electrically connected tothe semiconductor die 104A through the conductive wires 106 at theconnection terminals CT. In particular, the conductive wires 106 areelectrically connected to the conductive elements 110A of theredistribution layer 110 through the connection terminals CT (of bondingpads 105). Conductive terminals 118 are then formed on theredistribution layer 110, and being electrically connected to theconductive elements 110A.

Referring to FIG. 2F, after the formation of the redistribution layer110 and the conductive terminals 118, a plurality of conductive balls120 are placed onto the conductive terminals 118. The conductiveterminals 118 and the conductive balls 120 may, for example, be formedby a ball placement process and a reflow process. After placing theconductive balls 120 on the conductive terminals 118, a dicing orsingulation process is performed on the package structure illustrated inFIG. 2F to render a plurality of individual packages 100′ as shown inFIG. 2G. The dicing process is, for example, performed at the dicingline DL for singulation of the individual packages 100′.

Referring to FIG. 2G, the individual packages 100′ includes anencapsulant 108, a stacked die 104A, a plurality of bonding pads 105, aplurality of conductive wires 106, a redistribution layer 110 and aplurality of conductive balls 120. The encapsulant 108 has a top surface108A and a bottom surface 108B opposite to the top surface 108A. Thestack die 104A is embedded in the encapsulant 108. The bonding pads 105are embedded in the encapsulant 108, wherein connection terminals CT ofthe bonding pads 105 are exposed on a top surface 108A of theencapsulant 108. The conductive wires 106 are embedded in theencapsulant 108, wherein the stacked die 104A is electrically connectedto the bonding pads 105 through the conductive wires. The redistributionlayer 110 is disposed on the stacked die 104A and on the top surface108A of the encapsulant 108, wherein the redistribution layer 110 iselectrically connected to the stacked die 104A through the bonding pads105 and the conductive wires 106.

In the exemplary embodiment, the stacked die (semiconductor die 104A)has a first surface S1 exposed through the encapsulant 108. Theconnection terminals CT of the bonding pads 105 are coplanar with thefirst surface S1 of the stacked die 104A and the top surface 108A of theencapsulant 108. Furthermore, the stacked die 104A may include a firstdie (first semiconductor die) 104A-1, a second die (second semiconductordie) 104A-2 and a third die (third semiconductor die) 104A-3. The firstdie 104A-1 has the first surface S1 exposed through the encapsulant 108.The second die 104A-2 is stacked on the first die 104A-1 opposite to aside of the first surface S1. The second die 104A-2 cover portions ofthe first die 104A-1, and other portions of the first die 104A-1 notcovered by the second die 104A-2 contain die pads DP (bonding pads 105).The die pads DP of the first die 104A-1 are electrically connected tothe bonding pads 105 through the conductive wires 106. In addition, thethird die 104A-3 is stacked on the second die 104A-2, the third die104A-3 cover portions of the second die 104A-2, and other portions ofthe second die 104A-2 not covered by the third die 104A-3 contain diepads DP, the die pads DP of the second die 104A-2 are electricallyconnected to the bonding pads 105 through the conductive wires 106.

In the embodiment shown in FIG. 2G, the individual packages 100′ furtherincludes at least one passive component 115 embedded in the encapsulant108. However, it construes no limitation in the invention. Inalternative embodiments, the passive components 115 may be disposed onthe redistribution layer 110. Furthermore, in the exemplary embodiment,the encapsulant 108 has a first thickness 108T, and the redistributionlayer 110 has a second thickness 110T smaller than the first thickness108T. That is, the encapsulant 108 provides a first rigidity, and theredistribution layer 110 provides a second rigidity, wherein the firstrigidity is greater than the second rigidity. In addition, the bondingpads 105 are arranged with a first pitch P and the conductive balls 120are arranged with a second pitch P2, the second pitch P2 is greater thanthe first pitch P1. That is, the individual packages 100′ are directedto fan-out packages. The first pitch P and the second pitch P2 iscalculated based on a center position of the bonding pads 105 and theconductive balls 120.

In the embodiments shown above, the sacrificial structures are used tofix the position of the conductive wires. As such, when removing thesacrificial structure, the precise location of the wire or weld may beprovided for further connection. Furthermore, a thickness of thesemiconductor die may be effectively controlled during the thinningprocess, thus an overall size of the package structure may be reduced.In addition, with the presence of the sacrificial structure, an arearatio between the dies and the encapsulant is decreased. Thus, the issueof wafer or panel warpage may be resolved. Accordingly, the simplicityof the manufacturing process of the package structure may be realized,thereby reducing the overall manufacturing cost.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncovers modifications and variations of this invention provided fallwithin the scope of the following claims and their equivalents.

1. A manufacturing method of a package structure, comprising: providinga carrier, disposing a semiconductor die and at least one sacrificialstructure on the carrier; electrically connecting the semiconductor dieto bonding pads on the sacrificial structure through a plurality ofconductive wires; forming an encapsulant on the carrier to encapsulatethe semiconductor die, the sacrificial structure and the conductivewires; debonding the carrier, removing at least a portion of thesacrificial structure through a thinning process; and forming aredistribution layer on the semiconductor die and the encapsulant, theredistribution layer is electrically connected to the semiconductor diethrough the conductive wires.
 2. The manufacturing method of a packagestructure according to claim 1, wherein the sacrificial structure isdisposed on the carrier, and the semiconductor die is disposed on thesacrificial structure.
 3. The manufacturing method of a packagestructure according to claim 2, wherein a width of the sacrificialstructure is greater than a width of the semiconductor die.
 4. Themanufacturing method of a package structure according to claim 2,wherein the redistribution layer is formed on the semiconductor die andthe encapsulant after the removal of the sacrificial structure, and aplurality of passive components is disposed on the redistribution layer.5. The manufacturing method of a package structure according to claim 1,wherein the thinning process removes a portion of the semiconductor dieto form a thinned semiconductor die.
 6. The manufacturing method of apackage structure according to claim 1, wherein the bonding pads or theconductive wires are revealed after the thinning process.
 7. Themanufacturing method of a package structure according to claim 1,wherein a plurality of the sacrificial structures is disposed on thecarrier to surround the semiconductor die.
 8. The manufacturing methodof a package structure according to claim 7, wherein the semiconductordie and the sacrificial structures are disposed on a same plane and on asame surface of the carriers.
 9. The manufacturing method of a packagestructure according to claim 7, further comprising: forming a pluralityof passive components on the sacrificial structures, wherein theencapsulant is formed to encapsulate the passive components.
 10. Themanufacturing method of a package structure according to claim 9,wherein the redistribution layer is formed on the semiconductor die andthe encapsulant after the removal of the sacrificial structure, and theredistribution layer is electrically connected to the semiconductor dieand the passive components.
 11. A package structure, comprising: anencapsulant having a top surface and a bottom surface opposite to thetop surface; a stacked die embedded in the encapsulant; a plurality ofbonding pads of a sacrificial structure encapsulated by the encapsulant,wherein connection terminals of the bonding pads are exposed on a topsurface of the encapsulant; a plurality of conductive wires embedded inthe encapsulant, each of the plurality of conductive wires having oneend coupled to the stacked die and another end coupled to a terminal ofthe bonding pads opposite the connection terminals; a redistributionlayer, directly formed on a first surface of the stacked die exposedthrough the encapsulant, the connection terminals of the bonding pads,and the top surface of the encapsulant, the redistribution layer iselectrically connected to the stacked die through the bonding pads andthe conductive wires, wherein the connection terminals of the bondingpads, the first surface of the stacked die, and the top surface of theencapsulant are coplanar to each other.
 12. The package structureaccording to claim 11, further comprising at least one passive componentembedded in the encapsulant.
 13. The package structure according toclaim 11, further comprising at least one passive component disposed onthe redistribution layer.
 14. The package structure according to claim11, wherein the encapsulant has a first thickness, and theredistribution layer has a second thickness smaller than the firstthickness.
 15. The package structure according to claim 14, wherein theencapsulant provides a first rigidity, and the redistribution layerprovides a second rigidity, the first rigidity is greater than thesecond rigidity.
 16. (canceled)
 17. The package structure according toclaim 11, wherein the stacked die comprises: a first die having a firstsurface exposed through the encapsulant; a second die stacked on thefirst die opposite to a side of the first surface, the second die coverportions of the first die, and other portions of the first die notcovered by the second die contain die pads, the die pads of the firstdie are electrically connected to the bonding pads through theconductive wires.
 18. The package structure according to claim 17,wherein the stacked die further comprises: a third die stacked on thesecond die, the third die cover portions of the second die, and otherportions of the second die not covered by the third die contain diepads, the die pads of the second die are electrically connected to thebonding pads through the conductive wires.
 19. The package structureaccording to claim 11, further comprising a plurality of conductiveballs disposed on the redistribution layer.
 20. The package structureaccording to claim 19, wherein the bonding pads are arranged with afirst pitch and the conductive balls are arranged with a second pitch,the second pitch is greater than the first pitch.